Spartan-3E FPGA: Analogue Capture

Quad Serial DAC, up to 200KHz

Figure 9-5 provides the UCF constraints for the DAC interface, including the I/O pin

assignment and the I/O standard used.

NET “SPI_MISO” LOC = “N10″ | IOSTANDARD = LVCMOS33 ;

NET “SPI_MOSI” LOC = “T4″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET “SPI_SCK” LOC = “U16″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET “DAC_CS” LOC = “N8″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET “DAC_CLR” LOC = “P8″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

Dual ADC maybe up to 3MHz

Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.

NET “SPI_MOSI” LOC = “T4″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET “AMP_CS” LOC = “N7″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET “SPI_SCK” LOC = “U16″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET “AMP_SHDN” LOC = “P7″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET “AMP_DOUT” LOC = “E18″ | IOSTANDARD = LVCMOS33 ;

Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.

NET “AD_CONV” LOC = “P11″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET “SPI_SCK” LOC = “U16″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET “SPI_MISO” LOC = “N10″ | IOSTANDARD = LVCMOS33 ;