Spartan-3E FPGA LCD

LCD

Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin

assignment and the I/O standard used.

Figure 5-2: UCF Location Constraints for the Character LCD

NET “LCD_E” LOC = “M18″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “LCD_RS” LOC = “L18″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “LCD_RW” LOC = “L17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

# The LCD four-bit data interface is shared with the StrataFlash.

NET “SF_D<8>” LOC = “R15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<9>” LOC = “R16″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<10>” LOC = “P17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;