Spartan-3E FPGA: Strata Flash

Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration

image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit

StrataFlash. The Spartan-3E FPGA Starter Kit board ships with a 128 Mbit device. Address line SF_A24 is not used.

Figure 12-2: UCF Location Constraints for SPI Flash Connections

# some connections shared with SPI Flash, DAC, ADC, and AMP

NET “SPI_MISO” LOC = “N10″ | IOSTANDARD = LVCMOS33 ;

NET “SPI_MOSI” LOC = “T4″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET “SPI_SCK” LOC = “U16″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET “SPI_SS_B” LOC = “U3″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET “SPI_ALT_CS_JP11″ LOC = “R12″ | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

Note the shared pins with other functions.

Figure 11-2: UCF Location Constraints for StrataFlash Address Inputs

NET “SF_A<24>” LOC = “A11″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<23>” LOC = “N11″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<22>” LOC = “V12″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<21>” LOC = “V13″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<20>” LOC = “T12″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<19>” LOC = “V15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<18>” LOC = “U15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<17>” LOC = “T16″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<16>” LOC = “U18″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<15>” LOC = “T17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<14>” LOC = “R18″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<13>” LOC = “T18″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<12>” LOC = “L16″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<11>” LOC = “L15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<10>” LOC = “K13″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<9>” LOC = “K12″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<8>” LOC = “K15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<7>” LOC = “K14″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<6>” LOC = “J17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<5>” LOC = “J16″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<4>” LOC = “J15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<3>” LOC = “J14″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<2>” LOC = “J12″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<1>” LOC = “J13″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_A<0>” LOC = “H17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

Figure 11-3 provides the UCF constraints for the StrataFlash data pins, including the I/O

pin assignment and the I/O standard used.

NET “SF_D<15>” LOC = “T8″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<14>” LOC = “R8″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<13>” LOC = “P6″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<12>” LOC = “M16″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<11>” LOC = “M15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<10>” LOC = “P17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<9>” LOC = “R16″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<8>” LOC = “R15″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<7>” LOC = “N9″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<6>” LOC = “M9″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<5>” LOC = “R9″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<4>” LOC = “U9″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<3>” LOC = “V9″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<2>” LOC = “R10″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_D<1>” LOC = “P10″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SPI_MISO” LOC = “N10″ | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW ;

Figure 11-4 provides the UCF constraints for the StrataFlash control pins, including the

I/O pin assignment and the I/O standard used.

NET “SF_BYTE” LOC = “C17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_CE0″ LOC = “D16″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_OE” LOC = “C18″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_STS” LOC = “B18″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET “SF_WE” LOC = “D17″ | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;