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PIC ICD Implementation

Shamelessly copied from

Beyond Logic Microchip ICD documentation

The Magenta Icebreaker implements PIC Real Time Emulator using the facilities below.

A reserved bit in the config word is part 1 of magic:

bit 11: BKBUG: Background Debugger Mode (This bit documented as reserved in data sheet)
1 = Background debugger functions not enabled
0 = Background debugger functional.

Halting Execution:

To implement the MPLAB HALT feature, the debugger
must be entered when a high to low transition occurs on
the RB6 pin and the BKBUG configuration bit is programmed
to “0”. A edge detection circuit will generate a
HALT signal pulse when RB6 transitions from high to low.
The HALT signal will begin the HALT sequence. The
HALT signal must be sampled with Q4 to bound it to a
machine cycle.
Processor will go through what appears to be a normal
interrupt cycle. However, the normal interrupt logic in the
core cannot be used because the debugger would lose
the state of the GIE bit. This “debugger interrupt” must not
disturb the contents of the GIE bit nor fail to respond if the
GIE bit is “0”. The GIE bit must be available for restoration
after running debugger code. So, background debugger
logic will control sequencing of the key interrupt signals in
the core logic. The correctly timed HALT signal will be
OR’d with the NINTAKE signal to initiate the sequence.
When INBUG bit is set, this will need to block other signals
from setting NINTAKE, which will disable interrupts.
INBUG also prevents other HALTs from occurring. The
INTAK and INTAKD signals will control the vectoring. At
the same time, the background debugger logic external to
the core will begin counting cycles and sequencing
debugger related events. The INBUG bit will be set.
Freeze to the peripherals will be asserted, if the FREEZ
bit is set. The time that the freeze signal is asserted varies
depending on if the instruction finishing is a 1 or 2 cycle
instruction. When the interrupt vector is parallel loaded
into the PC, the background debugger logic will cause the
MSB PC<13> to be set. This will make the logic vector to
2004h instead of 0004h.
During this time, the BKA<12:0> register is updated with
the contents of the PC that was also loaded onto the
stack. This allows the background debugger to correctly
report the current (next to be executed) PC address.
Interrupts have to be automatically disabled when the
INBUG flag is set. Again, this must be independent of the
GIE bit.
As the processor vectors to 2004h, the CPU will fetch and
execute a “GOTO Bkg_Debug” instruction. The background
debugger logic will send a signal to the CPU core
that will cause the output of the PCLATH to assume the
value xxx11xxx. This ensures that the GOTO instruction
vectors to the highest page of memory without disturbing
the contents of the PCLATH.
So instead of taking the first instruction of the interrupt
handler a GOTO 1F00h will execute from 2004h. The
background debugger routine will commence. PCLATH
should be undisturbed, and the PC at breakpoint is at the
top of the stack.
The debugger software will use a RETURN instruction to
return to the mainline code. The RETURN will cause the
INBUG bit to be cleared and will also release the
FREEZE signal at the proper time.
The estimate is that the debugger code will take between
256 and 512 program memory words on the target system.
The vector for the start of debugger code is programmable
by placing the correct instruction in location 2004h.
Normally it will be a “GOTO 1F00h”.

Halting Execution by Breakpoint
Another HALT method is by breakpoint. As with any halt,
BKBUG configuration bit must be programmed to “0”. The
ICKBUG and BIGBUG registers contain a 13-bit value
that is compared against the current PC value. When the
values are equal and INBUG is not set, then the circuit will
generate a halt signal on that cycle. The HALT will commence
as with the external halt cycle.
Once the background debugger is entered, the
BKA<12:0> bits in the ICKBUG and BIGBUG registers
are loaded with the contents of the PC that was also
loaded onto the stack. This allows proper reporting of the
current state of the PC (next instruction to be executed)
when the background debugger is entered. The power up
and MCLR initialization state of these registers will be
0×0000, equal to the reset vector.
Disabling the breakpoints is implemented by setting
breakpoint address that lies in the address space of the
background debugger (like 0x1F00).

Single Stepping
Another HALT method is by single step. As with any halt,
BKBUG configuration bit must be programmed to “0”.
When the SSTEP bit is set, and the INBUG bit is cleared
signaling an exit of the debugger routine, the background
debugger logic will generate a HALT signal timed to allow
one instruction execution. The HALT will occur in the
FNOP cycle of the RETURN instruction. One user
instruction will be executed, then the device will re-enter
the background debugger routine in the same fashion as
the external halt.
To first get to a single step mode, the debugger must
enter normal run mode from reset, then enter the debugger
with an external halt. The SSTEP bit can be set and
then subsequently, any RETURN from the debugger will
be a single step execution.

Loss of Target System Resources
Using the background debugger causes some loss of
functionality in the users target system.
• RB6 and RB7 are lost to the user.
• The user must implement the ICSP logic in the system.
• One level of stack is lost to the debugger entry and
exit.
• Very low frequency systems may not work with the
debugger due to watchdog timer interrupts during
debugger code execution.
• User must allocate program space for the debug
monitor.